1. Field of the Invention
The present invention relates to memory devices based on phase change based memory materials, including chalcogenide based materials and on other programmable resistive materials, and methods for operating such devices.
2. Description of Related Art
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
In phase change memory, data is stored by causing transitions in an active region of the phase change material between amorphous and crystalline states. FIG. 1 is a graph of memory cells comprising phase change material and programmable to a plurality of resistance states including a high resistance reset (erased) state 102 and at least one lower resistance programmed (set) state 100, each state having non-overlapping resistance ranges.
The difference between the highest resistance R1 of the lower resistance state 100 and the lowest resistance R2 of the high resistance reset state 102 defines a read margin 101 used to distinguish cells in the lower resistance state 100 from those in the high resistance state 102. The data stored in a memory cell can be determined by determining whether the memory cell has a resistance corresponding to the lower resistance state 100 or to the high resistance state 102, for example by measuring whether the resistance of the memory cell is above or below a threshold resistance value RSA 103 within the read margin 101.
The change from the high resistance state 102 to the lower resistance state 100, referred to as set (or program) herein, is generally a lower current operation in which current heats the phase change material above a transition temperature to cause transition from the amorphous to the crystalline state. The change from lower resistance state 100 to the high resistance state 102, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous state.
In order to reliably distinguish between the high resistance state 102 and the lower resistance state 100, it is important to maintain a relatively large read margin 101. However, since the active region undergoes a phase change as a result of heating, during operation issues such as compositional changes in the phase change material within the active region can result in the formation of a high resistance interface within the electrical conduction path of the memory cell. This high resistance interface can result in a “set failure mode” in which the lower current set operation cannot successfully reduce the resistance of the memory cell below the threshold resistance value RSA, resulting in reliability issues and bit errors for those memory cells.
It is therefore desirable to provide a memory device and methods for operating such devices addressing the set failure mode and resulting in improved reliability and improved data storage performance.